The present invention relates to an MOS semiconductor integrated circuit including a current mirror circuit.
A conventional MOS semiconductor integrated circuit will be described with reference to FIGS. 6 to 8.
FIG. 6 is a circuit diagram of a current mirror circuit in a conventional MOS semiconductor integrated circuit. In FIG. 6, an output transistor N1R and an input transistor N1L, which is connected to operate as a diode, are both NMOS transistors and constitute an Nch current mirror circuit. On the other hand, an output transistor P2R and an input transistor P2L, which is connected to operate as a diode, are both PMOS transistors and constitute a Pch current mirror circuit functioning as an output current mirror circuit. The output of the Nch current mirror circuit is connected to the drain of the input transistor P2L of the Pch current mirror circuit.
The operation of the current mirror circuit shown in FIG. 6 will be described.
When a power supply voltage VDD is applied to the Nch current mirror circuit, input current Ii flowing through the input transistor N1L is mirrored by the output transistor N1R. The current flowing through the input transistor P2L of the Pch current mirror circuit, to which transistor the output of the Nch current mirror circuit is connected, is mirrored by the output transistor P2R. Output current Io, i.e., the mirrored current, is supplied by the Pch current mirror circuit.
Herein, the current amplification factors of the input transistor N1L and the output transistor N1R are denoted by .beta.L and .beta.R, respectively. Current equal to the product of the mirror ratio .beta.R/ .beta.L of the output and input transistors and the input current Ii flows through the output transistor N1R. Herein, the mirror ratio is assumed to be 1 for the sake of simplicity. In such a case, the current, which is equal to the input current Ii, flows through the output transistor N1R and drives the input transistor P2L of the Pch current mirror circuit connected to the output transistor N1R as a load thereof. The mirror ratio of the Pch current mirror circuit is also assumed to be 1 for the sake of simplicity. Then, the output current Io of the Pch current mirror circuit is equal to the input current Ii of the Nch current mirror circuit. By appropriately determining the mirror ratios of the respective current mirror circuits, the output current Io corresponding to the input current Ii can be supplied.
However, in this conventional configuration, if the power supply voltage is increased in an actual circuit, the current mirroring precision is deteriorated to a large degree. The reasons thereof will be described below.
FIG. 7 is a graph illustrating the Vds-Id characteristics between the drain-source voltage and the drain current of an NMOS transistor having a wide, long gate. In FIG. 7, the actually measured value of the threshold voltage is about 0.6 V. In the saturation region of the Vds-Id characteristics, as the drain-source voltage Vds increases, the drain current Id slightly increases.
For example, a case where the gate-source voltage Vgs is 1.2 V will be considered.
First, in a region where the drain-source voltage Vds is lower than the voltage at the output operation point A of the NMOS transistor, as the drain-source voltage Vds increases, the drain current Id slightly increases. If the gate-source voltage Vgs is 1.5 V, the increase of the drain current Id is more remarkable. The increase of the drain current Id in such a saturation region may be attributed to the short channel effects resulting from the expansion of a depletion layer in the gate in the vicinity of the drain in accordance with the increase of the drain-source voltage Vds.
Next, if the drain-source voltage Vds is higher than the output operation point A, as the drain-source voltage Vds increases, the drain current Id starts to greatly increase. This drastic increase can be explained by the phenomenon that hot electrons generated by a high electric field at the end of the drain of the NMOS transistor increases substrate current flowing from the drain directly into the substrate.
Because of these two reasons, the drain current Id cannot be kept constant in the saturation region. Thus, in a current mirror circuit using an MOS transistor having such characteristics as those illustrated in FIG. 7, since the drain current Id cannot be approximated at a constant value in the saturation region of the MOS transistor, the input current cannot be mirrored precisely.
The operation of the current mirror circuit shown in FIG. 6 will be described with reference to FIG. 7.
The input transistor N1L and the output transistor N1R both have a threshold voltage Vtn (=0.6 V) and exhibit the Vds-Id characteristics shown in FIG. 7. A gate-source voltage Vgs of 1.2 V is applied to both transistors. The input operation point (see FIG. 7) of the input transistor N1L is set at a drain-source voltage Vds (=1.2 V), which is a little higher than the threshold voltage Vtn. Herein, the threshold voltage of the input transistor P2L in the output current mirror circuit is denoted by Vtp.
If the power supply voltage VDD is 5 V, the output transistor N1R is designed to have a drain-source voltage Vds at a level slightly lower than VDD-Vtp (V), e.g., 3.6 V. The drain-source voltage Vds (=3.6 V) corresponds to the output operation point A (see FIG. 7) of the output transistor N1R. Thus, when the power supply voltage VDD is 5 V, the output transistor N1R operates at the output operation point A shown in FIG. 7. Accordingly, the drain current Id of the output transistor N1R has hardly increased from the drain current of the input transistor N1L, i.e., the input current Ii.
If the power supply voltage VDD is further increased to be set at 6.5 V, for example, the drain-source voltage Vds of the output transistor N1R becomes 5.1 V. The drain-source voltage Vds (=5.1 V) corresponds to the output operation point B (see FIG. 7) of the output transistor N1R. As can be understood from FIG. 7, the drain current of the output transistor N1R has increased from the input current Ii by about 10% in this case.
If the power supply voltage VDD is even more increased, then the drain-source voltage Vds of the output transistor N1R further increases and the drain current also increases. As a result, the output current Io of the Pch current mirror circuit drastically increases. Consequently, the mirror relationship collapses suddenly.
As described above, if the power supply voltage VDD is high, the conventional MOS semiconductor integrated circuit including a current mirror circuit cannot ensure sufficient mirror operation precision. Thus, the operability range of such an integrated circuit has an adversely low upper limit.
In order to improve the precision of such a current mirror circuit, a cascaded current mirror circuit is used. A cascaded current mirror circuit will be described with reference to FIG. 8.
FIG. 8 is a circuit diagram of a cascaded current mirror circuit. In FIG. 8, the same components as those of the current mirror circuit shown in FIG. 6 will be identified by the same reference numerals and the description thereof will be omitted herein.
NMOS transistors N1L' and N1R' are serially connected to the input and output transistors N1L and N1R, respectively, which constitute a current mirror circuit. The input transistor N1L' is diode-connected and the gate of the transistor N1L' is connected to the gate of the output transistor N1R'. In such a circuit configuration, the drain voltage VL' of the input transistor N1L can be substantially equalized with the drain voltage VR' of the output transistor N1R. Thus, the drain current of the transistors N1L and N1R, constituting the current mirror circuit, is hardly dependent on the drain voltage.
However, since the input operation point of the input transistor N1L is located at a drain-source voltage Vds (=1.2 V) slightly higher than the threshold voltage Vtn, the drain voltage VR' of the output transistor N1R, i.e., the source voltage of the transistor N1R' serially connected to the output transistor N1R, also becomes about 1.2 V. Thus, in the transistor N1R', the value of the power supply voltage VDD, at which the substrate current directly flowing from the drain to the substrate starts to increase, is higher than that of an ordinary current mirror circuit by as small as about 1.2 V. In other words, the cascaded current mirror circuit cannot expand the range of, i.e., increase the upper limit of, the power supply voltage VDD allowing for high-precision current mirroring by only about 1.2 V.